Sensitivity Analysis of Critical Parameters in Board Test

IN DESIGNING COMPLEX, highperformance boards, the designer must make several decisions: What surface-mount-technology (SMT) process should I use? What test escape rate is tolerable for custom ASICs (application-specific integrated circuits)? Is IEEE Std 1149.1 boundary scan necessary? What levels of board test coverage are best? If the designer failsto optimize these fundamental parameters of board manufacturing, test and repair costs will eat up the product's profits. On the other hand, ifthe designer minimizes incoming defect rates and carefully selects test coverage and isolation, test and repair costs decrease significantly. To make these decisions, designers need quantitative data on how quality and cost vary with defect rates and test coverage for boards with different SMT complexities. To obtain such data, we have conducted an analysis of the sensitivity of manufacturing quality and cost to the solder defect rate, the component functional defect rate, and solder defect test coverage. Board manufacturers typically mea-